The invention relates to a method of manufacturing a semiconductor device comprising a semiconductor body which is provided at a surface with a field-effect transistor having a gate insulated from the semiconductor body by a gate dielectric, and with a non-volatile memory element having a floating gate and a control gate, the floating gate being insulated from the semiconductor body by a floating gate dielectric and from the control gate by an inter-gate dielectric, by which method a first and a second active region of a first conductivity type adjoining the surface are defined in the semiconductor body for the transistor and the memory element, respectively, and the surface is coated with a first insulating layer providing the floating gate dielectric of the memory element, on which first insulating layer a silicon-containing layer is applied providing the floating gate of the memory element, after which source and drain zones of a second conductivity type of the memory element are provided in the semiconductor body and a second insulating layer is applied at the second active region so as to provide the inter-gate dielectric of the memory element, on which second insulating layer a conductive layer is applied providing the control gate of the memory element.
A method of manufacturing a semiconductor device of the kind mentioned in the opening paragraph is known from U.S. Pat. No. 5,340,764. In the known method, a first series of steps is performed to manufacture the non-volatile memory element consisting of two stacked layers of polycrystalline silicon (called poly hereinafter for short), which are mutually separated by an inter-gate dielectric and insulated from the semiconductor body by a floating gate oxide. After formation of the non-volatile memory element, a second series of steps is performed to manufacture the field-effect transistor. For this purpose a relatively thin gate oxide layer is applied, which is covered by a further poly layer providing the gate of the field-effect transistor. After patterning of, this poly layer, the field-effect transistor is provided with a source and a drain zone by means of a self-aligned implantation using the gate together with adjacent oxide field insulating regions as a mask.
Conventionally, a self-aligned implantation consists of an actual implantation of atoms into the semiconductor body followed by an anneal or so-called drive-in step, which is often carried out at a temperature as high as 1000.degree. C. in order to activate the as-implanted atoms and to repair implantation damage caused to the lattice of the semiconductor body.
A disadvantage of the known method is that the control gate and the inter-gate dielectric of the memory element as well as the gate and the gate dielectric of the transistor are applied prior to the self-aligned implantation of the source and the drain zone of the transistor, and, hence, are subjected to the high-temperature anneal following the actual implantation. Consequently, serious constraints are imposed on the choice of process compatible materials for the gate and the control gate as well as for the gate dielectric and the inter-gate dielectric. A further disadvantage of the known method is that it possesses a rather complex sequential character so as to achieve a separate device optimization for the non-volatile memory element and the field-effect transistor.